Arasan Chip Systems, Inc.
Arasan Chip Systems is a leading provider of Total IP solutions for mobile storage and connectivity applications.
- 408-471-4416
- 408-282-7800
- sales@arasan.com
- 2150 N. First St.
Suite 403
San Jose, CA 95131
United States of America
Categories
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product
Total Solution
SD 4.1 Family
To meet the ever increasing data transfer rate in high end applications, such as professional broadcasting transmission or advanced high resolution display, the SD 4.1 specification calls out the maximum performance of 1.56 Gbps at UHS-II full duplex mode per lane or half duplex UHS-II at 3.16 Gbps. In real applications, due to the system overhead and different SD 4.1 device controller designs, the actual measured performance can vary dramatically from system to system. With the newly introduced ADMA 3, the OS driver is now able to issue multiple read or multiple write commands at once, without having to wait for the SD controller to complete one command at a time. Once the SD host controller has collected multiple commands, it will then manage and complete them without intervention from the host software drive. Thus, the UHS-II 1.56 Gbps interface can be more effectively utilized and maximize the system throughput. This feature can be very useful when running multithreaded applications where multiple applications are constantly updating their status or swapping their contents by writing or reading small chunk of data to or from the memory card.
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Total MIPI Solutions
MIPI Standards starting with it's active participation as a Contributor to the MIPI Association in 2004 followed by the launch of the Industry First MIPI IP's the CSI, DSI and D-PHY IP Cores. With over 10 years of MIPI experience, Arasan has the broadest library and foundry history.
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MIPI Total Display IP Solution
DSI
The Arasan MIPI Display Serial Interface (DSI) Controller IP provides both device and host functionality. Additionally, the DSI Controller provides a high-speed serial interface between an application processor and display and follows a rigorous verification methodology to ensure interoperability of our DSI digital controller with our D-PHY analog IP. Arasan’s DSI solutions are MIPI standards-compliant and are designed to accelerate integration, lower risk and accelerate time to market for developers of display applications. Arasan’s expertise is backed by our unique silicon proven design discipline and product development process that ensures fast silicon success with our analog and digital IP.
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NAND Controller IP
ONFI
Arasan is the leading supplier of mobile storage IP and its products are used by most first tier memory suppliers. Arasan's deep experience with NAND flash memory interfaces and mobile storage standards began in 2001 when it joined the SD Association and shipped industry first SD card IP in 2003. Arasan is a current member of ONFI and JEDEC.
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MIPI Radio Front-End
RFFE
Mobile phone radios have developed into highly complex, multi-band and multi-standard designs that often have multiple radio frequency (RF) signal chains. The MIPI Alliance Specification for RF Front-End Control Interface (RFFE) was developed to offer a common and widespread method for controlling RF front-end devices. The RFFE Master IP core typically resides in the RFIC in a mobile platform, and utilizes the RFFE bus to identify, program and monitor the registers in RF front end Slave devices through programmed IO. It is designed to support existing standards such as LTE, UMTS, HSPA and EGPRS, and is usable in configurations ranging from single Master/single Slave to multi-Master/multi-Slave.
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MIPI Soundwire Total IP Solutions
Soundwire
Soundwire is suited for small, cost-sensitive audio peripherals such as modern digital class-D amplifiers and digital microphones. The Total MIPI SoundWire IP Solution from Arasan enables early adopters the fastest path to adoption of this new standard by offering a comprehensive IP package that includes the Verilog RTL source code for Master and Slave, fully validated for compliance with the standard, a comprehensive test environment with a compliance suite for verification of the IP package, a SoundWire Hardware Development Kit (“HDK”) for FPGA prototyping, a SoundWire protocol analyzer and a complete SoundWire software stack.
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MIPI I3C Sensor Controller
I3C
The main purpose of MIPI I3C is to standardize sensor communication, reduce the number of physical pins used in sensor system integration and support low-power, high-speed and other critical features supported by I2C and SPI.
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SD Card V.4.1 & UHS-II PHY
SD 4.1 Total Solution
To meet the ever increasing data transfer rate in high end applications, such as professional broadcasting transmission or advanced high resolution display, the SD 4.1 specification calls out the maximum performance of 1.56 Gbps at UHS-II full duplex mode per lane or half duplex UHS-II at 3.16 Gbps. In real applications, due to the system overhead and different SD 4.1 device controller designs, the actual measured performance can vary dramatically from system to system. With the newly introduced ADMA 3, the OS driver is now able to issue multiple read or multiple write commands at once, without having to wait for the SD controller to complete one command at a time. Once the SD host controller has collected multiple commands, it will then manage and complete them without intervention from the host software drive. Thus, the UHS-II 1.56 Gbps interface can be more effectively utilized and maximize the system throughput. This feature can be very useful when running multithreaded applications where multiple applications are constantly updating their status or swapping their contents by writing or reading small chunk of data to or from the memory card.
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SD Card
SD Card v.3.0 / eMMC v.4.51 IP Family
Designed for embedded applications that require high performance, small form factor, and high storage capacity, eMMC provides the support for embedded mass storage memory on embedded host systems. The eMMC protocol simplifies the access to NAND flash memories (such as MLC) to the host by hiding the functional differences among suppliers. Compliant to the latest JEDEC eMMC specifications, Arasan’s eMMC IP supports power-on-booting without the upper level software driver. The explicit sleep mode allows the host to instruct the controller to directly enter the sleep mode. The interface supports interface voltage of either 1.8V or 3.3V.
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PCIe End Point IP Core
The Arasan PCI Express End Point is a high-speed, high-performance, and low-power IP core that is fully compliant to the PCI Express Specification 1.1 and 2.0. The IP core is designed for applications in computing, networking, storage, servers, wireless, and consumer electronics. The feature-rich IP core is highly configurable that allows a target design to be implemented with the least number of gates and highest performance.
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Arasan PHY IP
Arasan PHY’s are readily available and in production with multiple foundries from 16nm to 180nm. Our PHY’s are designed for low power on the most advanced nodes for the mobile market while also targeting the automobile market on specialized nodes where extreme temperature tolerance is required.
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MIPI PHYs
Arasan MIPI PHY’s are readily available and in production with multiple foundries from 16nm to 180nm. Our PHY’s are designed for low power on the most advanced nodes for the mobile market while also targeting the automobile market on specialized nodes where extreme temperature tolerance is required.
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Semiconductors
Meets SDIO card v2.0 specificationSupports SDIO SPI, 1-bit, and 4-bit SD modesHost clock rate from 0-50 MHzSingle SDIO function interfaceSD commands processed in hardwareReset output on completion of initializationIndication of high speed and high power enabling to application logicMaximum block size supported is 1024 bytesThree I/O mode selection pinsCRC7 and CRC16 modulesSupports direct R/W (IO52) and extended R/W (IO53) commandsAPB bus interfaceParallel bus interfaceStandard 8051 split bus interfaceGeneric 8051 bus interfaceUART interface
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Ethernet
Arasan Chip Systems has a complete portfolio of Fast (10/100) Mbps and Gigabit (10/100/1000) Mbps and now 10Gigabit Ethernet IP. Our high quality IP has completed the rigorous interoperability tests at UNH-IOL laboratories and has been widely licensed. Arasan also provides a portable Ethernet driver.
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EMBEDDED MMC (EMMC)
SD 3.0 / eMMC 4.51 IP Family
The eMMC Host IP is an RTL design in Verilog that implements an MMC / eMMC host controller in an ASIC or FPGA. The core includes RTL code, test scripts and a test environment for full simulation verifications. The Arasan MMC / eMMC Host IP Core has been widely used in different MMC applications by major semiconductor vendors with proven silicon.
