Syntest Technologies
SynTest Technologies, Inc. was founded in January 1990 to develop and market technologically advanced test solutions for the electronics industry. The company shipped its first product in August 1991 and has maintained consistent growth and profitability every year since then. In addition to product sales, SynTest has established close partnerships with its customers to perform consulting services for specific designs, and to implement joint development projects based on customer specifications.
- 408-720-9956
- 408-720-9960
- support@syntest.com
- 4320 Stevens Creek Blvd
Suite 100
San Jose, CA 95129
United States of America
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product
Built-in Self-Test
TurboBIST
TurboBIST family of products from SynTest Technologies, Inc. includes tools for logic (TurboBIST - Logic) and memory (TurboBIST - Memory) (SRAM, ROM, DRAM and CAM) built-in self-test.
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Testability Analysis
TurboCheck
TurboScan is an advanced full-scan and partial-scan test suite. It includes a Scan Synthesizer and an Automatic Test Pattern Generator (ATPG). TurboScan automatically repairs testability violations to make your design highly testable.
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A Comprehensive Package of DFT Tools
DFT- PRO Plus
DFT-PRO Plus offers an integrated DFT solution covering scan synthesis and ATPG, memory Built-In Self-Test (BIST) synthesis and boundaryscan (BSD) synthesis. The corresponding tools generate RTL blocks that fit seamlessly into an existing synthesis flow
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Companion Tool to VS for Test Time & Pin reduction
UltraScan
UltraScan is SynTest's solution to combat increase in test time. In 130 nm or smaller ? nanometer geometries, many defects become delay defects and it becomes necessary to use delay tests to detect the transition faults and path delay faults. Often bridging tests are also required.
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Fault Simulation
Concurrent Fault Simulator
TurboFault combines high performance, versatility and accuracy. It is highly competitive with hardware accelerators for classical test fault grading. It supports synchronous and asynchronous designs at the gate level, including tri-state gates, latches, flip-flops, single and multi-port RAMs, complex bus resolution functions, and User Defined Primitives (UDPs).
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Framework for Soft-Error Protection
RobustScan™
RobustScan™ provides a platform for users to pick patented Configurable Soft-Error Resilience (CSER) cells or their preferred SER mitigation cells. First, Soft-Error Rate (SER) analysis is performed. Then it performs automatic robust-scan-cell and hardenedcombinational- cell selection and synthesis. Finally it generates verification testbenches for the final design. RobustScan™ can be used with scan chains inserted using third-party tools; it can be linked to third-party�s SER analysis programs and is fully compatible with SynTest�s existing DFT tools for test, debug, and diagnosis.
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Boundary Scan
TurboBSD
TurboBSD is SynTest high-performance Boundary Scan Designer. It is 100% compliant to the IEEE 1149.1 Boundary Scan Standard. TurboBSD performs Boundary Scan logic synthesis, creates BSDL (Boundary Scan Description Language) file, and generates Boundary Scan test patterns
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VS Tool Suite for Virtual Scan Synthesis and ATPG
VirtualScan
VirtualScan is SynTest's solution to combat increase in test data volume and test cycle volume. With VirtualScan (VS) an extremely large number of short scan chains within the SOC can be virtually accessed from outside the chip with a limited number of pins assigned as scan pins.
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Integration Tool Suite
TurboDFT
TurboDFT contains a suite of very useful and powerful DFT integration tools. TurboDFT allows users to automatically integrate and stitch DFT cores, whether they are created using DFT tools from SynTest or other vendors
