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JEDEC
semiconductor test methods and standards setting organization, Joint Electron Device Engineering Council.
See Also: UFS
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HBM Verification Tester
HBM-VT
High Power Pulse Instruments GmbH
- HBM pulse generator verification tester according ANSI/ESDA/JEDEC JS-001 up to ±10kV- To be used in HBM test and qualification labs for regular pulse generator specification compliance test in order to fulfill lab audit and certification requirements- Fully automatic compliance test and verification of HBM pulse generators regarding ANSI/ESDA/JEDEC JS-001 normative standard at 3 different load conditions: Short Circuit, 500 Ω, and a reference diode at VBR=15 V reverse breakdown voltage, including DC test- Parameter evaluation and verification of the transient HBM current waveforms: Peak Current, Rise Time, Decay Time, Maximum Ringing Current- Optionally available upgrade for all HPPI TLP-3010C, 4010C, 8010A, 8010C, HBM-TS10-A hardware systems in combination with HBM-S1-B (6kV) pulse generators (upgrade on request)- Fully automatic test report generation (PDF)- Electrically floating (no fixed system ground): The HBM loads, current sensor output, USB control interface and the enclosure are electrically floating. There is no limiting system ground which may introduce common-mode interference induced HBM current measurement errors.- Isolated industrial full-speed USB control interface- Isolated power supply derived from USB port- Compact size 126mm x 82.5mm x 44.5mm
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±6 kV ANSI/ESDA/JEDEC 2-Pin HBM Tester
HBM-S1-B
High Power Pulse Instruments GmbH
*±6 kV Human-Body-Model (HBM) 2-pin tester according ANSI/ESDA/JEDEC JS-001 standard with C = 100 pF, R = 1.5 kΩ discharge network*True HBM: the classical discharge network of the HBM-S1-A according the standard ensures compliant waveforms for all load conditions*Optionally available upgrade for all HPPI TLP-3010C, 4010C, 8010A, and 8010C hardware systems and software (upgrade on request)*Suppression of trailing pulses*Integrated 10 kΩ charge removal resistor*Integrated DUT voltage and DUT current sensor for real time voltage and current monitoring*Integrated DC test DUT switchIntegrated hardware 50 Ω trigger output for high speed digital oscilloscopesIntegrated overvoltage protection of voltage sense and DC test interfaces for oscilloscope and SMU protection during high voltage HBM testing*Fast and efficient HBM measurements including transient waveform data management using the HPPI TLP software*Compact size 145 mm x 82.5 mm x 44 mm
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Detective Logic Analyzer
DDR3
Provides logic analyzer like deep transaction Listing and Waveform captureCan store up to 1G of captured StatesContinuous, real time analysis, not post-processingEye Detector guarantees valid data acquisitionExtensive Triggering and Storage Qualification allows precise insightProtocol Violation Detector provides hundreds of simultaneous, real time tests to JEDEC specificationsRow Hammer Analysis for potential data corruptionInteractions among up to 8 ranks, over two slots are analyzed.Mode Register Listing providedSupports Auto-Clock rate detect and clock stoppage Connects to the target under test with DIMM, SO-DIMM, and BGA interposers or a midbus probeIntegrated Microsoft Charts gives quick insight into large trace capturesTrigger In & Out allows the Detective to integrate with other test tools
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DIP-to-JEDEC TO Adaptor Socket
1109522 & 1109523
DIP to TO Adapter Sockets. 8 pin DIP IC socket on the top and a circular, 8 pin TO can male pin footprint on the bottom. ICs now available only in 8 pin DIPs can be readily mounted on boards having TO thru-hole footprints without having to redesign the board.
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Climate Control Test Chamber
ACMAS's Climate Test Chamber is ideally suited for specimen test requiring quick changes of temperature. It covers various applications from JEDEC and IEC test standards. ACMAS Thermal Cyclic Chamber is equipped with advanced technology such as specimen temperature control which allows linear specimen temperature rates of change during rapid thermal cycling or accurate temperature ramp control. This chamber is also known as Climatic Test Chamber and Climate Controlled Test Chamber.
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SD Card
SD Card v.3.0 / eMMC v.4.51 IP Family
Designed for embedded applications that require high performance, small form factor, and high storage capacity, eMMC provides the support for embedded mass storage memory on embedded host systems. The eMMC protocol simplifies the access to NAND flash memories (such as MLC) to the host by hiding the functional differences among suppliers. Compliant to the latest JEDEC eMMC specifications, Arasan’s eMMC IP supports power-on-booting without the upper level software driver. The explicit sleep mode allows the host to instruct the controller to directly enter the sleep mode. The interface supports interface voltage of either 1.8V or 3.3V.
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test measurement unit
ITC59100 Rg/Qg
The ITC59100 Test Measurement Unit (TMU), which plugs into the ITC59000 Test Platform, performs gate charge (Qg) measurements that conform to MIL-STD-750C, Notice 2, Method 3471 and JEDEC Standard JESD24-2. In addition the ITC59100 TMU performs an internal gate resistance (Rg) test method that conforms to JEDEC Standard JESD24-11.
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IP Solution
eMMC 5.1
Demand for mobile content capacity and bandwidth for video, pictures and music is ever increasing. To address this demand in the next generation of smartphones, tablets, and portable devices, the eMMC 5.1 Specification from JEDEC, improves the current HS400 speeds operating at 3.2Gbps, with "command queuing" making the data transfers highly efficient by offloading the software overhead into the controller. eMMC 5.1 further improves the reliability of operation by utilizing an "enhanced strobe" at the PHY layer. The eMMC5.1 is backward compatible with the existing eMMC 4.51 and eMMC 5.0 Devices.
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ESD & Latch-Up Test Service
MASER Engineering has automatic test equipment for the most common ESD test pulse models. MIL - JEDEC - ESDA - IEC standards. IC level Human Body Model. IC level Machine Model. IC level Charged Device Model. System level IEC 61000 HBM. AEC-Q100 Field Induced Gate Leakage test. Static Latch-Up test. Dynamic Latch-Up test.
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DDR4 BGA Interposers, DDR4 DRAM X4/x8 Packages
N2114A
The N2114A DDR4 BGA interposers provide signal access to the clock, strobe, data, address and command signals to the DDR4 BGA package for making electrical and timing measurements with an Infiniium oscilloscope. With the DDR4 JEDEC specification defined at the DRAM ballout, the BGA probe adapter provides direct signal access to BGA package for true compliance testing.
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Rugged Half Slim SATA3
RunCore Innovation Technology Co. Ltd.
Standard Half Slim SATA SSD JEDEC MO-297.
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±6 kV ANSI/ESDA/JEDEC HBM Test System
HBM-TS10-A
High Power Pulse Instruments GmbH
*±6 kV Human-Body-Model (HBM) tester according ANSI/ESDA/JEDEC JS-001 standard with C = 100 pF, R = 1.5 kΩ discharge network*Wafer, package and system level HBM testing*True HBM: the classical discharge network of the HBM-S1-A according the standard ensures compliant waveforms for all load conditions*No trailing pulses*Integrated 10 kΩ charge removal resistor*Integrated DUT HBM current sensor for real time transient current monitoring with 1V/A output sensitivity into 50 Ω digital oscilloscope input*Integrated DUT HBM voltage sensor for real time transient voltage monitoring with 1/200V/V output sensitivity into 50 Ω digital oscilloscope input*Integrated overvoltage protection of the DUT voltage sensor, DUTcurrentsensor and DC test interface for efficient overload protection of the digital oscilloscope and SMU during high voltage HBM testing*Integrated DC test DUT switch with automatic switch control*Integrated 50 Ω precision hardware trigger output for high speed digital oscilloscopes*Fast HBM measurements, typically 0.5s per pulse including one-point DC measurement between pulses*Eficient sofware for system control and waveform data management (fully compatible with TLP measurement data)*The sofware can control automatic probers for fast measurements of complete wafers*Compact size 145 mm x 82.5 mm x 44 mm of the integrated HBM pulse generator probehead*System controller size 483 mm x 487 mm x 133 mm*High performance and high quality components*Optionally available hardware upgrades to all HPPI fully integrated HBM/HMM/TLP/VF-TLP test systems TLP-3010C, 4010C, 8010A, and 8010C
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ESD, Latch-up testing / design service
ESDdoctor
ESDdoctor consulting service can identify, diagnose, and solve any ESD/EOS problem quickly and definitively, at a surprisingly low entry cost. You can choose testing and diagnosis only, or add ESD design services to the consulting package. ESD, Latch-up testing: HBM (ANSI/ESDA and JEDEC) on packaged dies. MM (ANSI/ESDA and JEDEC) on packaged dies. Latch-up JEDEC on packaged dies TLP on packaged and bare dies.VF-TLP on bare dies.
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QFP-to-PGA JEDEC 132-Position, 0.025 [0.64] Pitch Adaptor
95-132I25
QFP to PGA Adapter for JEDEC 132 Position, .025 [.64] Pitch. Reduce costs by using less expensive QFP packages to replace PGA footprints in existing designs. Pins are mechanically fastened and soldered to board using Aries patented process, creating a reliable electrical connection and rugged contact.
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Analyzer Probes
The following probes are available for the MA51x0 and MA41x0 series analyzers. These probes are designed for low-voltage and high-speed midbus probing or probing with an interposer. The following JEDEC memory standards are widely used by these probes: DDR5 (JESD79-5), DDR4 (JESD79-4), DDR3 (JESD79-3), LPDDR5 & LPDDR5X (JESD209-5), LPDDR4 & LPDDR4X (JESD209-4), and LPDDR3 (JESD209-3).
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Memory Tester for DDR4 DIMMS
RAMCHECK LX
USBWith the RAMCHECK LX DDR4 memory tester package (part number INN-8686-DDR4) you can quickly test and identify DDR4 DIMMs that comply with JEDEC standards. Tests are fast, reliable and easy to do. The RAMCHECK LX DDR4 package includes the RAMCHECK LX base tester and 288-pin DDR4 DIMM adapter. (This package is also available with the DDR4 DIMM Pro adapter, featuring a very rugged test socket).
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NAND Controller IP
ONFI
Arasan is the leading supplier of mobile storage IP and its products are used by most first tier memory suppliers. Arasan's deep experience with NAND flash memory interfaces and mobile storage standards began in 2001 when it joined the SD Association and shipped industry first SD card IP in 2003. Arasan is a current member of ONFI and JEDEC.
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JEDEC TO Collet Socket
Series 514
TO Collet Sockets. Aries TO sockets feature molded chamfer lead-ins for easy device insertion. High stand-off design for heat dissipation and easy cleaning. External polarization for positive location.
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ESD & Latch-Up Test System
Identify and help correct ESD and latch-up susceptibility issues on sensitive integrated circuit components prior to full-scale production with the Thermo Scientific™ MK.2-SE ESD and Latch-Up Test System. The MK.2-SE test system provides advanced capabilities to test high pin count IC devices to Human Body Model (HBM) and Machine Model (MM) ESD standards. The system’s pulse delivery design addresses wave form hazards such as trailing pulse and pre-discharge voltage rise, and performs Latch-Up testing per the JEDEC EIA/JESD 78 Method.
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Programmable Read Only Memory (PROM)
Is a Static Random Access Memory. The pinout is the JEDEC 28 pin, 8-bit wide standard, which allows easy memory board layouts which accommodate a variety of industry standard ROM, PROM,EPROM, EEPROM and RAMs.
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ESD Testers
Hanwa Electronic Ind. Co.,Ltd.
◆Adaptable to the following international standard waveform;JEDEC, ESDA, AEC, and JEITA◆This system’s uniquely short discharge circuit is made possible by its original mechanical design.◆The short circuit minimizes the influence of inductance and capacitance on the data.◆The use of a single circuit ensures data stability for each device pin tested.
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Thermal Test Boards
Thermal Engineering Associates, Inc.
TEA offers a series of thermal test boards for package characterization and design comparison that conform to to the JEDEC JESD51 standards. The board family, referred to as the TTB-1000 series, consists of two different standard sizes designed to cover a wide range of package sizes. These boards, also referred to as test coupons, provide a well defined mounting environment, will withstand temperatures to 125 oC, and have lead lands terminated in eyelets to allow for hand-wired connection to the board edge contacts. The board mates with a dual 18-pin, 3.962 mm (0.156") pitch edge-card connector.
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Universal Flash Storage
UFS
Universal Flash Storage (UFS) is a JEDEC standard for high performance mobile storage devices suitable for next generation data storage. The UFS is also adopted by MIPI as a data transfer standard designed for mobile systems. Most UFS applications require large storage capacity for data and boot code. Applications include mobile phones, tablets, DSC, PMP, MP3, and other applications requiring mass storage, boot storage, XiP or external cards. The UFS standard is a simple, but high-performance, serial interface that efficiently moves data between a host processor and mass storage devices. USF transfers follow the SCSI model, but with a subset of SCSI commands.The Arasan UFS IP family consists of Host controller IP, Device controller IP, and MPHY.
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Post Wire and Die Bond Inspection Machine
IV-T3300
IV-T3300 is a post wire and die bond inspection machine with Dual JEDEC Tray Feeder System. It features a large inspection area of 600x500mm and a quick trays change of 5-7 seconds.
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Semiconductor Package Wind Tunnel
WT-100
Thermal Engineering Associates, Inc.
The WT-100 Forced Convection (Moving Air) Wind Tunnel is designed in accordance with the EIA/JEDEC JESD51-6 standard for thermal characterization of semiconductor packages and devices. The vertical design minimizes laboratory floor space requiements. Air is drawn in at the bottom and exhausts at the top. The test section is large enough to accommodate the largest JEDEC and SEMI thermal test boards. Air velocity can be adjusted over the range of 0.5 to 5 m/s; air velocity is monitored with an included hot-wire anemometer connected to a digital display. A Type-T thermocouple is mounted in the test section for monitoring the moving air temperature.
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LPDDR
A large number of LPDDR sockets have been developed to cover the wide variety of ball I/O configurations. This catalog supports the JEDEC 209 Standard configuration.
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Surface Mount-to-DIP JEDEC SOT-25, SOT-23A-6 Adaptor
1110748
Surface Mount to DIP Adapter for SOT-25, SOT-23A-6. Allows for breadboarding or substitution of microgate SOT-23A-6 and SOT-25 IC and transistor packages into .100 [2.54] pitch proto boards or PC boards. Solder masked top-side pads allow user to hand solder devices directly to topside of adapter with fewer problems of solder bridging. Longer male bottom pins are available at special request for easy use of probe clips. Large topside pads allow for soldering test pins, jumpers, etc. to top of adapter.
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mSAT SSD for Industrial Embedded Applications
mSATA SSD Series
ADLINK’s mSATA SSD Series with the SATA 6Gb/s interface is fully compliant with the standard mSATA form factor, also known as JEDEC MO300. Utilizing Toggle 2.0 MLC flash technology, capacities of up to 1TB are available with support for read/write speeds of up to 550MB/sec and 500MB/sec respectively . Additionally, the power consumption of the ADLINK’s mSATA modules is much lower than that of traditional hard drives.
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Detective Logic Analyzer
LPDDR5
Provides logic analyzer like deep transaction Listing and Waveform capture. Can store up to 512M of captured States at up to 6400+ MT/sContinuous, real time analysis, not post-processing 2D (voltage & time) Eye Detector guarantees valid data acquisition on each signalExtensive Triggering and Storage Qualification allows precise insightIndustry Leading Protocol Violation Detector provides hundreds of simultaneous, real time tests to JEDEC specifications, NOT post processing. No other tool can provide this!Mode Register Listing provided
